Accelerating Physics-Based BTI Modeling for Arbitrary Workloads Using Defect Ensemble and Time Compression Techniques

Abstract

We present a methodology to simulate bias temperature instability (BTI) for long-term reliability predictions and alternating current (AC) conditions. Our focus is on repetitive structure within the applied gate voltage (Vg) pulse. Throughout this work, we develop a set of different methodologies to simplify and substantially reduce computational demand for predictive BTI modeling on longer times scales than previously numerically feasible. To achieve this goal, we employ a compact representation of transition rates for complex sequences of subsequently applied gate voltages. This simplification enables efficient simulation of the threshold voltage shift ΔVth for periodical (with a possible extension to arbitrary) workloads. Besides this compression over time, we develop compression techniques over the defect ensemble, further accelerating simulation for periodical Vg signals. Using commercial quality planar nFETs subjected to BTI stress with a periodical gate voltage signal, we reproduce experimental ΔVth(t) traces (t is time), and achieve good agreement between experimental and simulation data with a significant speed-up compared to conventional BTI modeling. As a consequence, these methods are suitable for both practical, large-scale reliability simulations involving realistic lifetime workloads.