Publication:

Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?

Date

2019
Journal article
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dc.contributor.authorSimoen, Eddy
dc.contributor.authorO'Sullivan, Barry
dc.contributor.authorRitzenthaler, Romain
dc.contributor.authorDentoni Litta, Eugenio
dc.contributor.authorSchram, Tom
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorClaeys, Cor
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorO'Sullivan, Barry
dc.contributor.imecauthorRitzenthaler, Romain
dc.contributor.imecauthorDentoni Litta, Eugenio
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.contributor.orcidimecO'Sullivan, Barry::0000-0002-9036-8241
dc.contributor.orcidimecRitzenthaler, Romain::0000-0002-8615-3272
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.accessioned2021-10-27T18:23:04Z
dc.date.available2021-10-27T18:23:04Z
dc.date.embargo9999-12-31
dc.date.issued2019
dc.identifier.issn0268-1242
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/34010
dc.identifier.urlhttps://iopscience.iop.org/article/10.1088/1361-6641/aaf4dc
dc.source.beginpage15017
dc.source.issue1
dc.source.journalSemiconductor Science and Technology
dc.source.volume34
dc.title

Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?

dc.typeJournal article
dspace.entity.typePublication
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