On the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors

dc.contributor.author	Bellens, Rudi
dc.contributor.author	De Schrijver, Erik
dc.contributor.author	Van den Bosch, Geert
dc.contributor.author	Groeseneken, Guido
dc.contributor.author	Heremans, Paul
dc.contributor.author	Maes, Herman
dc.contributor.imecauthor	Van den Bosch, Geert
dc.contributor.imecauthor	Groeseneken, Guido
dc.contributor.imecauthor	Heremans, Paul
dc.contributor.orcidimec	Van den Bosch, Geert::0000-0001-9971-6954
dc.date.accessioned	2021-09-29T12:39:45Z
dc.date.available	2021-09-29T12:39:45Z
dc.date.embargo	9999-12-31
dc.date.issued	1994
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/28
dc.source.beginpage	413
dc.source.endpage	419
dc.source.issue	3
dc.source.journal	IEEE Transactions on Electron Devices
dc.source.volume	41
dc.title	On the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors
dc.type	Journal article
dspace.entity.type	Publication
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