Publication:

Buried silicon-germanium pMOSFETs: experimental analysis in VLSI logic circuits under aggressive voltage scaling

Date

2012
Journal article
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dc.contributor.authorCrupi, Felice
dc.contributor.authorAlioto, Massimo
dc.contributor.authorFranco, Jacopo
dc.contributor.authorMagnone, Paolo
dc.contributor.authorKaczer, Ben
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorMitard, Jerome
dc.contributor.authorWitters, Liesbeth
dc.contributor.authorHoffmann, Thomas Y.
dc.contributor.imecauthorFranco, Jacopo
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.imecauthorMitard, Jerome
dc.contributor.imecauthorWitters, Liesbeth
dc.contributor.orcidimecFranco, Jacopo::0000-0002-7382-8605
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecMitard, Jerome::0000-0002-7422-079X
dc.date.accessioned2021-10-20T10:26:13Z
dc.date.available2021-10-20T10:26:13Z
dc.date.embargo9999-12-31
dc.date.issued2012
dc.identifier.issn1063-8210
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20514
dc.source.beginpage1487
dc.source.endpage1495
dc.source.issue8
dc.source.journalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
dc.source.volume20
dc.title

Buried silicon-germanium pMOSFETs: experimental analysis in VLSI logic circuits under aggressive voltage scaling

dc.typeJournal article
dspace.entity.typePublication
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