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A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link

Date

2011
Proceedings Paper
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dc.contributor.authorRooseleer, Bram
dc.contributor.authorCosemans, Stefan
dc.contributor.authorDehaene, Wim
dc.contributor.imecauthorRooseleer, Bram
dc.contributor.imecauthorCosemans, Stefan
dc.contributor.imecauthorDehaene, Wim
dc.date.accessioned2021-10-19T18:16:05Z
dc.date.available2021-10-19T18:16:05Z
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19705
dc.identifier.urlhttp://dx.doi.org/10.1109/ESSCIRC.2011.6044936
dc.source.beginpage519
dc.source.conference37th European Solid-State Circuits Conference - ESSCIRC
dc.source.conferencedate12/09/2011
dc.source.conferencelocationHelsinki Finland
dc.source.endpage522
dc.title

A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link

dc.typeProceedings paper
dspace.entity.typePublication
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