Publication:

Selective etch process for fab-compatible top contacts, replacement oxide, and interlayer removal in 2D FETs

Date

2025
Proceedings Paper
https://doi.org/10.1109/iedm50572.2025.11353796
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dc.contributor.authorSmets, Quentin
dc.contributor.authorSchram, Tom
dc.contributor.authorvan Dorp, Dennis
dc.contributor.authorJiang, Yuchao
dc.contributor.authorOpdebeeck, Ann
dc.contributor.authorCott, Daire
dc.contributor.authorSebaai, Farid
dc.contributor.authorMorin, Pierre
dc.contributor.authorGovoreanu, Bogdan
dc.contributor.authorPanarella, Luca
dc.contributor.authorKozhakhmetov, A.
dc.contributor.authorDorow, C. J.
dc.contributor.authorOni, A.
dc.contributor.authorO'Brien, K. P.
dc.contributor.authorAvci, U.
dc.contributor.authorLockhart de la Rosa, Cesar Javier
dc.contributor.authorKar, Gouri Sankar
dc.date.accessioned2026-07-23T08:55:14Z
dc.date.available2026-07-23T08:55:14Z
dc.date.createdwos2026
dc.date.issued2025
dc.description.abstractTwo rarely used features of Transition Metal Dichalcogenides (TMDs) are their exceptional chemical stability in some wet etchants and their unique anisotropic van der Waals structure. These are leveraged to selectively recess the oxide cap, and fabricate 2D FETs with damascene-type top contacts on monolayer WS2, MoS2, and multilayer WSe2 in a 300mm pilot line. In addition, the process is extended to a replacement oxide stack, and interlayer selective removal is demonstrated using liquid intercalation, reducing the top gate CET from 2.5 to 1.5nm. These form three new fundamental building blocks for 2D integration technology.
dc.description.wosFundingTextThe authors thank the TMD, ALD, 2D transfer, TEM teams, P. Kumar, W. De Wever, V. Kumar, L. S. Nemarugommula, T. Van Opstal, S. Ghosh, R. Verheyen, B. Storms, S. Arnauts and the 300mm process support and characterization teams. This research was funded by the imec IIAP Exploratory Logic program, the 2D-PL pilot line project through Horizon Europe (101189797) and Horizon 2020 (952792) grant agreements.
dc.identifier.doi10.1109/iedm50572.2025.11353796
dc.identifier.isbn979-8-3315-6786-6
dc.identifier.issn2380-9248
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59912
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceIEEE International Electron Devices Meeting (IEDM)
dc.source.conferencedate2025-12-06
dc.source.conferencelocationSan Francisco
dc.source.journal2025 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, IEDM
dc.source.numberofpages4
dc.title

Selective etch process for fab-compatible top contacts, replacement oxide, and interlayer removal in 2D FETs

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-07-14
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-07-14
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