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Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology
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Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology
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Date
1997
Proceedings Paper
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1720.pdf
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Bock, Karlheinz
;
Russ, Christian
;
Badenes, Gonçal
;
Groeseneken, Guido
;
Deferm, Ludo
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2
since deposited on 2021-09-30
Acq. date: 2025-12-10
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1936
since deposited on 2021-09-30
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Acq. date: 2025-12-10
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Downloads
2
since deposited on 2021-09-30
Acq. date: 2025-12-10
Views
1936
since deposited on 2021-09-30
3
last month
Acq. date: 2025-12-10
Citations