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Circuit design for bias compatibility investigation of bulk FinFET based floating body RAM

Date

2009
Proceedings Paper
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dc.contributor.authorAnchlia, Ankur
dc.contributor.authorGarcia Bardon, Marie
dc.contributor.authorPoliakov, Pavel
dc.contributor.authorRooseleer, Bram
dc.contributor.authorDe Wachter, Bart
dc.contributor.authorCollaert, Nadine
dc.contributor.authorvan der Zanden, Koen
dc.contributor.authorMiranda Corbalan, Miguel
dc.contributor.authorDehaene, Wim
dc.contributor.authorVerkest, Diederik
dc.contributor.imecauthorGarcia Bardon, Marie
dc.contributor.imecauthorRooseleer, Bram
dc.contributor.imecauthorDe Wachter, Bart
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorDehaene, Wim
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.accessioned2021-10-17T21:17:49Z
dc.date.available2021-10-17T21:17:49Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/14899
dc.source.conferenceIEEE Workshop on Memory Technology, Design and Testing
dc.source.conferencedate31/08/2009
dc.source.conferencelocationHsinchu Taiwan
dc.title

Circuit design for bias compatibility investigation of bulk FinFET based floating body RAM

dc.typeProceedings paper
dspace.entity.typePublication
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