Publication:

Design enablement of CFET devices for sub-2nm CMOS nodes

Date

2022-05-19
Proceedings Paper
https://doi.org/10.23919/DATE54114.2022.9774720
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dc.contributor.authorZografos, Odysseas
dc.contributor.authorChehab, Bilal
dc.contributor.authorSchuddinck, Pieter
dc.contributor.authorMirabelli, Gioele
dc.contributor.authorKakarla, Naveen
dc.contributor.authorXiang, Yang
dc.contributor.authorWeckx, Pieter
dc.contributor.authorRyckaert, Julien
dc.contributor.imecauthorZografos, Odysseas
dc.contributor.imecauthorChehab, Bilal
dc.contributor.imecauthorSchuddinck, Pieter
dc.contributor.imecauthorMirabelli, Gioele
dc.contributor.imecauthorKakarla, Naveen
dc.contributor.imecauthorXiang, Yang
dc.contributor.imecauthorWeckx, Pieter
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.orcidimecZografos, Odysseas::0000-0002-9998-8009
dc.contributor.orcidimecMirabelli, Gioele::0000-0001-7060-4836
dc.contributor.orcidimecXiang, Yang::0000-0003-0091-6935
dc.contributor.orcidimecSchuddinck, Pieter::0000-0003-1893-3135
dc.date.accessioned2023-04-28T08:00:01Z
dc.date.available2022-07-17T02:27:36Z
dc.date.available2022-09-06T12:44:28Z
dc.date.available2023-04-28T08:00:01Z
dc.date.embargo2022-05-31
dc.date.issued2022-05-19
dc.identifier.doi10.23919/DATE54114.2022.9774720
dc.identifier.eisbn978-3-9819263-6-1
dc.identifier.issn1530-1591
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40127
dc.publisherIEEE
dc.source.beginpage29
dc.source.conference25th Design, Automation and Test in Europe Conference and Exhibition (DATE)
dc.source.conferencedateMAR 14-23, 2022
dc.source.conferencelocationAntwerp, Belgium
dc.source.endpage33
dc.source.journalDATE2022 Proceedings
dc.source.numberofpages5
dc.subject.disciplineElectrical & electronic engineering
dc.subject.keywordsCMOS scaling, CFET
dc.title

Design enablement of CFET devices for sub-2nm CMOS nodes

dc.typeProceedings paper
dspace.entity.typePublication
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