Publication:
Pathfinding: A design methodology for fast exploration and optimization of 3D-stacked integrated circuits
Date
| dc.contributor.author | Milojevic, Dragomir | |
| dc.contributor.author | Radojcic, Riko | |
| dc.contributor.author | Carpenter, R. | |
| dc.contributor.author | Marchal, Pol | |
| dc.contributor.author | Van der Plas, Geert | |
| dc.contributor.imecauthor | Milojevic, Dragomir | |
| dc.contributor.imecauthor | Van der Plas, Geert | |
| dc.contributor.orcidimec | Van der Plas, Geert::0000-0002-4975-6672 | |
| dc.date.accessioned | 2021-10-18T00:48:50Z | |
| dc.date.available | 2021-10-18T00:48:50Z | |
| dc.date.issued | 2009-10 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/15863 | |
| dc.source.conference | International Symposium System-on-Chip - SoC | |
| dc.source.conferencedate | 7/10/2009 | |
| dc.source.conferencelocation | Tampere Finland | |
| dc.title | Pathfinding: A design methodology for fast exploration and optimization of 3D-stacked integrated circuits | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
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