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Impact of Back-side Power Delivery Network Layout on the FinFET Device Performance

Date

2022-10-01
Proceedings Paper
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dc.contributor.authorArutchelvan, Goutham
dc.contributor.authorChiarella, Thomas
dc.contributor.authorArimura, Hiroaki
dc.contributor.authorVeloso, Anabela
dc.contributor.authorJourdain, Anne
dc.contributor.authorDentoni Litta, Eugenio
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorMitard, Jerome
dc.contributor.imecauthorArutchelvan, Goutham
dc.contributor.imecauthorChiarella, Thomas
dc.contributor.imecauthorArimura, Hiroaki
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorJourdain, Anne
dc.contributor.imecauthorDentoni Litta, Eugenio
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.imecauthorMitard, Jerome
dc.contributor.orcidimecChiarella, Thomas::0000-0002-6155-9030
dc.contributor.orcidimecDentoni Litta, Eugenio::0000-0003-0333-376X
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.contributor.orcidimecMitard, Jerome::0000-0002-7422-079X
dc.contributor.orcidimecArimura, Hiroaki::0000-0002-3138-708X
dc.contributor.orcidimecJourdain, Anne::0000-0002-7610-0513
dc.date.accessioned2024-01-25T15:58:03Z
dc.date.available2023-02-02T10:21:48Z
dc.date.available2024-01-25T15:58:03Z
dc.date.embargo9999-12-31
dc.date.issued2022-10-01
dc.identifier.issn0000-0000
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/41054
dc.source.conferenceInternational Conference on Solid State Devices and Materials
dc.source.conferencedate01/10/22
dc.source.conferencelocationJapan
dc.source.journalno
dc.source.numberofpages1
dc.subject.disciplineElectrical & electronic engineering
dc.title

Impact of Back-side Power Delivery Network Layout on the FinFET Device Performance

dc.typeProceedings paper
dspace.entity.typePublication
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