Publication:

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out

Date

2022
Proceedings Paper
https://doi.org/10.1109/AICAS54282.2022.9869993
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dc.contributor.authorSingh, Abhairaj
dc.contributor.authorZahedi, Mahdi
dc.contributor.authorShahroodi, Taha
dc.contributor.authorGupta, Mohit
dc.contributor.authorGebregiorgis, Anteneh
dc.contributor.authorKomalan, Manu
dc.contributor.authorJoshi, Rajiv, V
dc.contributor.authorCatthoor, Francky
dc.contributor.authorBishnoi, Rajendra
dc.contributor.authorHamdioui, Said
dc.contributor.imecauthorGupta, Mohit
dc.contributor.imecauthorKomalan, Manu
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecGupta, Mohit::0000-0002-1924-1264
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2023-02-23T12:48:17Z
dc.date.available2022-11-05T02:53:45Z
dc.date.available2022-11-17T09:47:18Z
dc.date.available2023-02-23T12:48:17Z
dc.date.embargo9999-12-31
dc.date.issued2022
dc.description.wosFundingTextThis work was supported by EU H2020 grant "DAIS'' that received funding from ECSEL Joint Undertaking (JU) under grant agreement No 101007273.
dc.identifier.doi10.1109/AICAS54282.2022.9869993
dc.identifier.eisbn978-1-6654-0996-4
dc.identifier.issnN/A
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40681
dc.publisherIEEE
dc.source.beginpage451
dc.source.conferenceIEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) - Intelligent Technology in the Post-Pandemic Era
dc.source.conferencedateJUN 13-15, 2022
dc.source.conferencelocationIncheon
dc.source.endpage454
dc.source.journalN/A
dc.source.numberofpages4
dc.subject.keywordsARRAY
dc.subject.keywordsMEMORY
dc.title

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out

dc.typeProceedings paper
dspace.entity.typePublication
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