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Memory technology for the terabit era: from 2D to 3D

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dc.contributor.authorVan Houdt, Jan
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.date.accessioned2021-10-24T16:21:08Z
dc.date.available2021-10-24T16:21:08Z
dc.date.embargo9999-12-31
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/29704
dc.identifier.urlhttps://ieeexplore.ieee.org/document/7998186/
dc.source.beginpageT2-1
dc.source.conferenceIEEE Symposium on VLSI Technology
dc.source.conferencedate5/06/2017
dc.source.conferencelocationKyoto Japan
dc.title

Memory technology for the terabit era: from 2D to 3D

dc.typeProceedings paper
dspace.entity.typePublication
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