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A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibrationn in 28nm digital CMOS

Date

2013
Proceedings Paper
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dc.contributor.authorVerbruggen, Bob
dc.contributor.authorIriguchi, Masao
dc.contributor.authorde la Guia, Manuel
dc.contributor.authorGlorieux, Guy
dc.contributor.authorDeguchi, Kazuaki
dc.contributor.authorMalki, Badr
dc.contributor.authorCraninckx, Jan
dc.contributor.imecauthorGlorieux, Guy
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.accessioned2021-10-21T13:59:30Z
dc.date.available2021-10-21T13:59:30Z
dc.date.embargo9999-12-31
dc.date.issued2013
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23320
dc.source.beginpageC268
dc.source.conferenceSymposium on VLSI Circuits
dc.source.conferencedate11/06/2013
dc.source.conferencelocationKyoto Japan
dc.source.endpageC269
dc.title

A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibrationn in 28nm digital CMOS

dc.typeProceedings paper
dspace.entity.typePublication
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