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Characterization and otimalization of 65nm CMOS technology using scanning spreading resistance microscopy

Date

2005
Meeting abstract
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dc.contributor.authorEyben, Pierre
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorChramtsov, I.
dc.contributor.authorFouchier, M.
dc.contributor.authorJanssens, Tom
dc.contributor.authorVandervorst, Wilfried
dc.contributor.imecauthorEyben, Pierre
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorVandervorst, Wilfried
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.date.accessioned2021-10-16T01:32:56Z
dc.date.available2021-10-16T01:32:56Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10444
dc.source.beginpage55
dc.source.conferenceProceedings of the 8th Int. Workshop on the Fabrication , Characterization and Modeling of Ultra Shallow Junctions in Semicond.
dc.source.conferencedate5/06/2005
dc.source.conferencelocationDaytona Beach, FL USA
dc.title

Characterization and otimalization of 65nm CMOS technology using scanning spreading resistance microscopy

dc.typeMeeting abstract
dspace.entity.typePublication
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