Chips with multiple interconnected dies in a package offer significant advantages over those with only a single monolithic die and this is driving the rapid adoption of multi-die packages in the market. In such packages, die-to-die interconnects are typically realized as large, dense arrays of fine-pitch micro-bumps or hybrid bonds, prone to manufacturing defects like shorts and opens. To address this, typically some spare interconnects are included to "repair" defective ones. This paper introduces an Interconnect Repair Language (IRL), based on Google’s Protocol Buffers, to describe all repair provisions. It also presents benefit/cost metrics for evaluation of a repair solution. As benefit metric, we use the spare and repair ratios, while costs are expressed as additional silicon area and propagation delay. We illustrate IRL and the various metrics with a running example from UCIe-Advanced 2.0. Finally, the paper presents a list of potential EDA tools based on the proposed IRL.
