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70 nm fully-depleted SOI cmos using a new fabrication scheme: the spacer/replacer scheme

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dc.contributor.authorvan Meer, Hans
dc.contributor.authorDe Meyer, Kristin
dc.contributor.imecauthorDe Meyer, Kristin
dc.date.accessioned2021-10-14T23:37:50Z
dc.date.available2021-10-14T23:37:50Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6952
dc.source.beginpage170
dc.source.conferenceSymposium on VLSI Technology: Digest of Technical Papers
dc.source.conferencedate11/06/2002
dc.source.conferencelocationHonolulu, HI USA
dc.source.endpage171
dc.title

70 nm fully-depleted SOI cmos using a new fabrication scheme: the spacer/replacer scheme

dc.typeProceedings paper
dspace.entity.typePublication
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