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Algorithm and Architecture Co-optimization for Digital Enhancements of Deep Submicron CMOS Transceivers

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dc.contributor.authorLi, Chunshu
dc.contributor.thesisadvisorVan der Perre, Liesbet
dc.contributor.thesisadvisorPollin, Sofie
dc.contributor.thesisadvisorVerhelst, Marian
dc.date.accessioned2021-10-23T12:10:27Z
dc.date.available2021-10-23T12:10:27Z
dc.date.issued2016-01
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26900
dc.identifier.urlhttps://limo.libis.be/primo-explore/fulldisplay?docid=LIRIAS1733140&context=L&vid=Lirias&search_scope=Lirias&tab=default_tab&lang=en_US&fromSitemap=1
dc.title

Algorithm and Architecture Co-optimization for Digital Enhancements of Deep Submicron CMOS Transceivers

dc.typePHD thesis
dspace.entity.typePublication
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