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CMOS-Fabricated Ring Surface Ion Trap with TSV Integration

 
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0002-4850-9354
cris.virtualsource.department44999307-3622-4542-94ae-888bfbd005d3
cris.virtualsource.orcid44999307-3622-4542-94ae-888bfbd005d3
dc.contributor.authorZhao, Peng
dc.contributor.authorLim, Yu Dian
dc.contributor.authorLi, Hongyu
dc.contributor.authorLikforman, Jean-Pierre
dc.contributor.authorGuidoni, Luca
dc.contributor.authorDesormeaux, Lilay Gros
dc.contributor.authorTan, Chuan Seng
dc.date.accessioned2026-06-03T09:44:08Z
dc.date.available2026-06-03T09:44:08Z
dc.date.createdwos2026-03-24
dc.date.issued2023
dc.description.abstractWe present the design, fabrication, and test of ring surface trap on 12-inch wafers with a CMOS process. The design is based on Through Silicon Vias (TSV) interconnects. Up to 200 ions were loaded and cooled; preliminary compensations of electrostatic potential imperfections show that rotational symmetry can be partially restored.
dc.description.wosFundingTextThis research was co-supported by ANR-NRF Joint Grant Call NRF2020-NRF-ANR073 HIT. We acknowledge the fabrication support from IME and AMF, Singapore.
dc.identifier.doi10.1109/iedm45741.2023.10413875
dc.identifier.issn2380-9248
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59527
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceInternational Electron Devices Meeting (IEDM)
dc.source.conferencedate2023-12-09
dc.source.conferencelocationSan Francisco
dc.source.journal2023 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM
dc.source.numberofpages4
dc.title

CMOS-Fabricated Ring Surface Ion Trap with TSV Integration

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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