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Towards a Computationally Efficient Verilog-A Defect-Centric BTI Compact Model for Circuit Aging Simulations

 
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cris.virtual.orcid0000-0002-0356-0973
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cris.virtual.orcid0000-0002-1016-8654
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cris.virtual.orcid0000-0002-1484-4007
cris.virtualsource.department5d1a73c2-f82f-43a0-9af2-32fb15f176bf
cris.virtualsource.department34c59f3a-5b4c-42cc-aac3-f7242ce5bdf6
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cris.virtualsource.departmentde93b028-9708-4f3a-99f0-5edbf35f1ef2
cris.virtualsource.department812f2909-a81b-4593-9b32-75331cffa35c
cris.virtualsource.orcid5d1a73c2-f82f-43a0-9af2-32fb15f176bf
cris.virtualsource.orcid34c59f3a-5b4c-42cc-aac3-f7242ce5bdf6
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cris.virtualsource.orcidde93b028-9708-4f3a-99f0-5edbf35f1ef2
cris.virtualsource.orcid812f2909-a81b-4593-9b32-75331cffa35c
dc.contributor.authorSangani, Dishant
dc.contributor.authorClaes, Dieter
dc.contributor.authorWeckx, Pieter
dc.contributor.authorKaczer, Ben
dc.contributor.authorGielen, Georges
dc.date.accessioned2026-01-29T10:14:17Z
dc.date.available2026-01-29T10:14:17Z
dc.date.createdwos2025-10-18
dc.date.issued2025
dc.description.abstractComplex physics-based models have been developed with the capability to capture typical BTI features like recovery, time-dependent variability and long-term saturation. However, for a successful EDA compact model, other practical criteria like stability (convergence) and computational efficiency are just as important as those functional features. In this paper, we perform a study a previously published Verilog-A based BTI model from the perspective of practical feasibility. To that end, (i) we analyze the computational performance of the BTI model, and (ii) we achieve an optimal trade-off between accuracy and computational efficiency with a newly proposed methodology for reducing the number of traps.
dc.identifier.doi10.1109/IRPS48204.2025.10983507
dc.identifier.isbn979-8-3315-0478-6
dc.identifier.issn1541-7026
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/58755
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.beginpageN/A
dc.source.conference2025 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS
dc.source.conferencedate2025-03-30
dc.source.conferencelocationMonterey
dc.source.journal2025 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS
dc.source.numberofpages6
dc.title

Towards a Computationally Efficient Verilog-A Defect-Centric BTI Compact Model for Circuit Aging Simulations

dc.typeProceedings paper
dspace.entity.typePublication
imec.identified.statusLibrary
imec.internal.crawledAt2025-10-22
imec.internal.sourcecrawler
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