An Efficient Reconfigurable Neural Network on Chip

dc.contributor.author	Khalil, Kasem
dc.contributor.author	Dey, Bappaditya
dc.contributor.author	Abdelrehim, Mostafa
dc.contributor.author	Kumar, Ashok
dc.contributor.author	Bayoumi, Magdy
dc.contributor.imecauthor	Dey, Bappaditya
dc.contributor.orcidimec	Dey, Bappaditya::0000-0002-0886-137X
dc.date.accessioned	2022-08-23T10:15:34Z
dc.date.available	2022-05-05T02:17:49Z
dc.date.available	2022-07-08T09:31:53Z
dc.date.available	2022-08-23T10:15:34Z
dc.date.issued	2021
dc.identifier.doi	10.1109/ICECS53924.2021.9665619
dc.identifier.eisbn	978-1-7281-8281-0
dc.identifier.isbn	978-1-7281-8281-0
dc.identifier.issn	978-1-7281-9493-6
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/39756
dc.publisher	IEEE
dc.source.conference	28th IEEE International Conference on Electronics, Circuits, and Systems (IEEE ICECS)
dc.source.conferencedate	NOV 28-DEC 01, 2021
dc.source.conferencelocation	Dubai
dc.source.journal	2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
dc.source.numberofpages	4
dc.subject.keywords	HIGH-PERFORMANCE
dc.subject.keywords	LOW-POWER
dc.subject.keywords	ON-CHIP
dc.title	An Efficient Reconfigurable Neural Network on Chip
dc.type	Proceedings paper
dspace.entity.type	Publication
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