Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study

dc.contributor.author	Kaczer, Ben
dc.contributor.author	Degraeve, Robin
dc.contributor.author	Rasras, Mahmoud
dc.contributor.author	De Keersgieter, An
dc.contributor.author	Van de Mieroop, Koen
dc.contributor.author	Groeseneken, Guido
dc.contributor.imecauthor	Kaczer, Ben
dc.contributor.imecauthor	Degraeve, Robin
dc.contributor.imecauthor	De Keersgieter, An
dc.contributor.imecauthor	Groeseneken, Guido
dc.contributor.orcidimec	Kaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimec	De Keersgieter, An::0000-0002-5527-8582
dc.date.accessioned	2021-10-14T21:58:59Z
dc.date.available	2021-10-14T21:58:59Z
dc.date.embargo	9999-12-31
dc.date.issued	2002
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/6461
dc.source.beginpage	555
dc.source.endpage	564
dc.source.issue	4_5
dc.source.journal	Microelectronics Reliability
dc.source.volume	42
dc.title	Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study
dc.type	Journal article
dspace.entity.type	Publication
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