Publication:
A low energy clustered instruction memory hierarchy for long instruction word processors
Date
| dc.contributor.author | Jayapala, Murali | |
| dc.contributor.author | Barat, Francisco | |
| dc.contributor.author | Op de Beeck, P. | |
| dc.contributor.author | Catthoor, Francky | |
| dc.contributor.author | Deconinck, G. | |
| dc.contributor.author | Corporaal, Henk | |
| dc.contributor.imecauthor | Jayapala, Murali | |
| dc.contributor.imecauthor | Catthoor, Francky | |
| dc.contributor.orcidimec | Jayapala, Murali::0000-0001-7917-0149 | |
| dc.contributor.orcidimec | Catthoor, Francky::0000-0002-3599-8515 | |
| dc.date.accessioned | 2021-10-14T21:54:32Z | |
| dc.date.available | 2021-10-14T21:54:32Z | |
| dc.date.issued | 2002 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/6434 | |
| dc.source.beginpage | 258 | |
| dc.source.conference | Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 12th International Workshop, PATMOS | |
| dc.source.conferencedate | 11/09/2002 | |
| dc.source.conferencelocation | Sevilla Spain | |
| dc.source.endpage | 267 | |
| dc.title | A low energy clustered instruction memory hierarchy for long instruction word processors | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| Files | ||
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