Publication:
Wafer-Level LICCDM Device Testing
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0002-0356-0973 | |
| cris.virtual.orcid | 0000-0002-3623-1842 | |
| cris.virtual.orcid | 0000-0002-8390-6785 | |
| cris.virtual.orcid | 0000-0002-6481-2951 | |
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| cris.virtualsource.orcid | 894d712a-328b-43e9-8331-871ceac6a4e6 | |
| cris.virtualsource.orcid | a9297c9a-1d0e-40a3-a8a8-5edf6176ec9a | |
| cris.virtualsource.orcid | e0386a23-f2bf-4f53-a36f-c1380bca0db7 | |
| dc.contributor.author | Simicic, Marko | |
| dc.contributor.author | Wu, Wei-Min | |
| dc.contributor.author | Claes, Dieter | |
| dc.contributor.author | Tamura, Shinichi | |
| dc.contributor.author | Shimada, Yohei | |
| dc.contributor.author | Sawada, Masanori | |
| dc.contributor.author | Chen, Shih-Hung | |
| dc.contributor.imecauthor | Simicic, Marko | |
| dc.contributor.imecauthor | Wu, Wei-Min | |
| dc.contributor.imecauthor | Claes, Dieter | |
| dc.contributor.imecauthor | Chen, Shih-Hung | |
| dc.contributor.orcidimec | Simicic, Marko::0000-0002-3623-1842 | |
| dc.date.accessioned | 2022-06-28T14:01:15Z | |
| dc.date.available | 2022-05-05T02:17:41Z | |
| dc.date.available | 2022-05-16T07:58:45Z | |
| dc.date.available | 2022-06-28T14:01:15Z | |
| dc.date.embargo | 9999-12-31 | |
| dc.date.issued | 2021 | |
| dc.description.abstract | With the integrated circuit technology evolution towards 25D and 3D stacking, wafer-level and bare-die-level electrostatic discharge testing is becoming a necessity. In this work, we use our Low-Impedance Contact CDM tester to measure integrated circuit products and assess the possibilities and potential issues of CDM testing of wafers and bare dies. | |
| dc.identifier.doi | 10.23919/eos/esd52038.2021.9574789 | |
| dc.identifier.eisbn | 978-1-58537-329-1 | |
| dc.identifier.isbn | 978-1-58537-330-7 | |
| dc.identifier.issn | 0739-5159 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/39751 | |
| dc.publisher | IEEE | |
| dc.source.conference | 43rd Annual EOS/ESD Symposium (EOS/ESD) | |
| dc.source.conferencedate | 2021-NaN | |
| dc.source.conferencelocation | Tucson | |
| dc.source.journal | 43rd Annual EOS/ESD Symposium (EOS/ESD) | |
| dc.source.numberofpages | 8 | |
| dc.subject.discipline | Electrical & electronic engineering | |
| dc.title | Wafer-Level LICCDM Device Testing | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| Files | Original bundle
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