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A parallel for loop memory template for a high level synthesis compiler

Date

2010
Proceedings Paper
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dc.contributor.authorMoore, Craig
dc.contributor.authorDevos, Harald
dc.contributor.authorStroobandt, Dirk
dc.date.accessioned2021-10-18T19:17:17Z
dc.date.available2021-10-18T19:17:17Z
dc.date.embargo9999-12-31
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17652
dc.source.beginpage449
dc.source.conferenceEuromicro Symposium on Digital Systems Design - DSD
dc.source.conferencedate1/09/2010
dc.source.conferencelocationLille France
dc.title

A parallel for loop memory template for a high level synthesis compiler

dc.typeProceedings paper
dspace.entity.typePublication
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