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Transistor optimisation for a low-cost, high-performance 0.13 μm CMOS technology

Date

2001
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dc.contributor.authorAugendre, Emmanuel
dc.contributor.authorKubicek, Stefan
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorMertens, S.
dc.contributor.authorLindsay, Richard
dc.contributor.authorVerbeeck, Rita
dc.contributor.authorVan Laer, Joris
dc.contributor.authorDupas, Luc
dc.contributor.authorBadenes, Gonçal
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorVerbeeck, Rita
dc.contributor.imecauthorVan Laer, Joris
dc.contributor.imecauthorDupas, Luc
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.date.accessioned2021-10-14T16:36:17Z
dc.date.available2021-10-14T16:36:17Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5019
dc.source.conference2nd ULIS Workshop on Ultimate Integration of Silicon; 2001;
dc.source.conferencelocation
dc.title

Transistor optimisation for a low-cost, high-performance 0.13 μm CMOS technology

dc.typeOral presentation
dspace.entity.typePublication
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