Publication:
Double-gate FinFETs as a CMOS technology downscaling option: an RF perspective
Date
| dc.contributor.author | Nuttinck, Sebastien | |
| dc.contributor.author | Parvais, Bertrand | |
| dc.contributor.author | Curatola, Gilberto | |
| dc.contributor.author | Mercha, Abdelkarim | |
| dc.contributor.imecauthor | Parvais, Bertrand | |
| dc.contributor.imecauthor | Mercha, Abdelkarim | |
| dc.contributor.orcidimec | Parvais, Bertrand::0000-0003-0769-7069 | |
| dc.contributor.orcidimec | Mercha, Abdelkarim::0000-0002-2174-6958 | |
| dc.date.accessioned | 2021-10-16T18:13:25Z | |
| dc.date.available | 2021-10-16T18:13:25Z | |
| dc.date.issued | 2007-02 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/12628 | |
| dc.source.beginpage | 279 | |
| dc.source.endpage | 283 | |
| dc.source.issue | 2 | |
| dc.source.journal | IEEE Trans. ELectron Devices | |
| dc.source.volume | 54 | |
| dc.title | Double-gate FinFETs as a CMOS technology downscaling option: an RF perspective | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
| Files | ||
| Publication available in collections: |