Publication:

50 nm high performance strained Si/SiGe pMOS devices with multiple quantum wells

Date

2002
Proceedings Paper
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dc.contributor.authorCollaert, Nadine
dc.contributor.authorVerheyen, Peter
dc.contributor.authorDe Meyer, Kristin
dc.contributor.authorLoo, Roger
dc.contributor.authorCaymax, Matty
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorVerheyen, Peter
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.imecauthorLoo, Roger
dc.contributor.imecauthorCaymax, Matty
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimecLoo, Roger::0000-0003-3513-6058
dc.date.accessioned2021-10-14T21:15:50Z
dc.date.available2021-10-14T21:15:50Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6127
dc.source.beginpage15
dc.source.conferenceVLSI Nanoelectronics Workshop
dc.source.conferencedate9/06/2002
dc.source.conferencelocationHonolulu, HI USA
dc.source.endpage16
dc.title

50 nm high performance strained Si/SiGe pMOS devices with multiple quantum wells

dc.typeProceedings paper
dspace.entity.typePublication
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