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A 3.6pJ/access 480MHz, 128Kbit on-chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability.

Date

2008
Proceedings Paper
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dc.contributor.authorCosemans, S.
dc.contributor.authorDehaene, Wim
dc.contributor.authorCatthoor, Francky
dc.contributor.imecauthorDehaene, Wim
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2021-10-17T06:38:06Z
dc.date.available2021-10-17T06:38:06Z
dc.date.embargo9999-12-31
dc.date.issued2008
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13562
dc.source.beginpage278
dc.source.conference34th European Solid-State Circuits Conference - ESSCIRC
dc.source.conferencedate15/09/2008
dc.source.conferencelocationEdinburgh UK
dc.source.endpage281
dc.title

A 3.6pJ/access 480MHz, 128Kbit on-chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability.

dc.typeProceedings paper
dspace.entity.typePublication
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