Publication:
A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs
| dc.contributor.author | Sateesan, Arish | |
| dc.contributor.author | Sinha, Sharad | |
| dc.contributor.author | Smitha, K. G. | |
| dc.contributor.author | Vinod, A. P. | |
| dc.contributor.orcidext | Sateesan, Arish::0000-0002-8197-0097 | |
| dc.date.accessioned | 2022-03-08T14:19:14Z | |
| dc.date.available | 2022-03-08T14:19:14Z | |
| dc.date.issued | 2021 | |
| dc.identifier.doi | 10.1007/s11063-021-10458-1 | |
| dc.identifier.issn | 1370-4621 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/39365 | |
| dc.publisher | SPRINGER | |
| dc.source.beginpage | 2331 | |
| dc.source.endpage | 2377 | |
| dc.source.issue | 3 | |
| dc.source.journal | NEURAL PROCESSING LETTERS | |
| dc.source.numberofpages | 47 | |
| dc.source.volume | 53 | |
| dc.title | A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs | |
| dc.type | Journal article review | |
| dspace.entity.type | Publication | |
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