Understanding and Modeling the Impact of Defects on Electrical Characteristics of Si/SiGe Heterostructures at Cryogenic temperatures

Abstract

Si/SiGe heterostructures are a promising platform for electron spin based quantum computers. In this work, we show that the dielectric trapping of these devices can be studied with a phenomenological approach based on employment of effective charges at channel interfaces. We consider a device as consisting of two independent channels: one in the Si quantum well and another one in the Si capping layer. For each channel we use compact models to extract the respective characteristics including the threshold voltage, gate oxide capacitance, and channel mobility. By employing these parameters in our device simulator, we can model the hysteretic capacitance-voltage and current-voltage characteristics at cryogenic temperatures. Within this methodology, we extract a mobility value of both the Si quantum well and the interface channel and correlate them with defect density and barrier thickness. Next, we evaluate the interface state energy distribution, which shows a strong peak around 0.2 eV below the conduction band minimum and a peak value of 4 × 1013 cm−2eV−1. Our interface state energy distribution profiles are in good agreement with those reported in the literature, which supports our hypothesis that the hysteresis is driven by interface traps.