Publication:

An ultra-thin hybrid floating gate concept for sub-20nm NAND flash technologies

Date

2011
Proceedings Paper
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dc.contributor.authorWellekens, Dirk
dc.contributor.authorBlomme, Pieter
dc.contributor.authorRosmeulen, Maarten
dc.contributor.authorSchram, Tom
dc.contributor.authorCacciato, Antonio
dc.contributor.authorVan Aerde, Steven
dc.contributor.authorDebusschere, Ingrid
dc.contributor.authorVan Houdt, Jan
dc.contributor.imecauthorWellekens, Dirk
dc.contributor.imecauthorBlomme, Pieter
dc.contributor.imecauthorRosmeulen, Maarten
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorVan Aerde, Steven
dc.contributor.imecauthorDebusschere, Ingrid
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.orcidimecRosmeulen, Maarten::0000-0002-3663-7439
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.date.accessioned2021-10-19T21:46:08Z
dc.date.available2021-10-19T21:46:08Z
dc.date.embargo9999-12-31
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20143
dc.source.beginpage22
dc.source.conference3rd International memory Workshop - IMW
dc.source.conferencedate22/05/2011
dc.source.conferencelocationMonterey, CA USA
dc.source.endpage25
dc.title

An ultra-thin hybrid floating gate concept for sub-20nm NAND flash technologies

dc.typeProceedings paper
dspace.entity.typePublication
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