Publication:

On MOS admittance modeling to study border trap capture/emission and its effect on electrical behavior of high-k/III-V MOS devices

Date

2015
Journal article
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dc.contributor.authorVais, Abhitosh
dc.contributor.authorMartens, Koen
dc.contributor.authorLin, Dennis
dc.contributor.authorCollaert, Nadine
dc.contributor.authorMocuta, Anda
dc.contributor.authorDe Meyer, Kristin
dc.contributor.authorThean, Aaron
dc.contributor.imecauthorVais, Abhitosh
dc.contributor.imecauthorMartens, Koen
dc.contributor.imecauthorLin, Dennis
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecVais, Abhitosh::0000-0002-0317-7720
dc.contributor.orcidimecMartens, Koen::0000-0001-7135-5536
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.date.accessioned2021-10-22T23:50:26Z
dc.date.available2021-10-22T23:50:26Z
dc.date.issued2015
dc.identifier.issn0167-9317
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26029
dc.identifier.urlhttp://www.sciencedirect.com/science/article/pii/S0167931715003123
dc.source.beginpage227
dc.source.endpage230
dc.source.journalMicroelectronic Engineering
dc.source.volume147
dc.title

On MOS admittance modeling to study border trap capture/emission and its effect on electrical behavior of high-k/III-V MOS devices

dc.typeJournal article
dspace.entity.typePublication
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