Publication:

Ultimate Layer Stacking Technology for High Density Sequential 3D Integration

 
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0001-5490-0416
cris.virtual.orcid0000-0002-2412-0176
cris.virtualsource.department9f04b13f-f81c-4d48-a5bd-0b2cb5210392
cris.virtualsource.departmentc4b1f5eb-c9a2-40f7-9503-91a2a00bb0cb
cris.virtualsource.orcid9f04b13f-f81c-4d48-a5bd-0b2cb5210392
cris.virtualsource.orcidc4b1f5eb-c9a2-40f7-9503-91a2a00bb0cb
dc.contributor.authorRadu, I.
dc.contributor.authorNguyen, B-Y.
dc.contributor.authorChang, C-H.
dc.contributor.authorNeve, C. Roda
dc.contributor.authorGaudin, G.
dc.contributor.authorBesnard, G.
dc.contributor.authorBatude, P.
dc.contributor.authorLoup, V.
dc.contributor.authorBrunet, L.
dc.contributor.authorVandooren, Anne
dc.contributor.authorHoriguchi, Naoto
dc.date.accessioned2026-04-27T14:31:25Z
dc.date.available2026-04-27T14:31:25Z
dc.date.createdwos2026-03-24
dc.date.issued2023
dc.description.abstractA review of wafer-level stacking technology providing a ultra thin and uniform single-crystalline silicon film onto a device wafer is reported in this paper. Smart Cut™ technology has been adapted at low temperatures for the transfer of a thin Si layer - ready for device fabrication. The surface micro-roughness is below 0.2nm and film thickness uniformity of 0.4nm within wafer and wafer-to-wafer measurements. Combining with low temperature device processing, the sequential manufacturing of 3D devices is demonstrated. Although the maximum temperature of the sequential 3D process does not exceed 500°C, the transistor characteristics are preserved. In this paper we report for the first time demonstration of Smart Cut layer stacking below 400°C.
dc.description.wosFundingTextThis work has been partially supported by the European funding program IPCEI, The development of low temperature Smart Cut is performed at Substrate innovation Center, jointly supported by Soitec and CEA LETI.
dc.identifier.doi10.1109/iedm45741.2023.10413807
dc.identifier.issn2380-9248
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59223
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceInternational Electron Devices Meeting (IEDM)
dc.source.conferencedate2023-12-09
dc.source.conferencelocationSan Francisco
dc.source.journal2023 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM
dc.source.numberofpages4
dc.title

Ultimate Layer Stacking Technology for High Density Sequential 3D Integration

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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