Publication:
Ultimate Layer Stacking Technology for High Density Sequential 3D Integration
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0001-5490-0416 | |
| cris.virtual.orcid | 0000-0002-2412-0176 | |
| cris.virtualsource.department | 9f04b13f-f81c-4d48-a5bd-0b2cb5210392 | |
| cris.virtualsource.department | c4b1f5eb-c9a2-40f7-9503-91a2a00bb0cb | |
| cris.virtualsource.orcid | 9f04b13f-f81c-4d48-a5bd-0b2cb5210392 | |
| cris.virtualsource.orcid | c4b1f5eb-c9a2-40f7-9503-91a2a00bb0cb | |
| dc.contributor.author | Radu, I. | |
| dc.contributor.author | Nguyen, B-Y. | |
| dc.contributor.author | Chang, C-H. | |
| dc.contributor.author | Neve, C. Roda | |
| dc.contributor.author | Gaudin, G. | |
| dc.contributor.author | Besnard, G. | |
| dc.contributor.author | Batude, P. | |
| dc.contributor.author | Loup, V. | |
| dc.contributor.author | Brunet, L. | |
| dc.contributor.author | Vandooren, Anne | |
| dc.contributor.author | Horiguchi, Naoto | |
| dc.date.accessioned | 2026-04-27T14:31:25Z | |
| dc.date.available | 2026-04-27T14:31:25Z | |
| dc.date.createdwos | 2026-03-24 | |
| dc.date.issued | 2023 | |
| dc.description.abstract | A review of wafer-level stacking technology providing a ultra thin and uniform single-crystalline silicon film onto a device wafer is reported in this paper. Smart Cut™ technology has been adapted at low temperatures for the transfer of a thin Si layer - ready for device fabrication. The surface micro-roughness is below 0.2nm and film thickness uniformity of 0.4nm within wafer and wafer-to-wafer measurements. Combining with low temperature device processing, the sequential manufacturing of 3D devices is demonstrated. Although the maximum temperature of the sequential 3D process does not exceed 500°C, the transistor characteristics are preserved. In this paper we report for the first time demonstration of Smart Cut layer stacking below 400°C. | |
| dc.description.wosFundingText | This work has been partially supported by the European funding program IPCEI, The development of low temperature Smart Cut is performed at Substrate innovation Center, jointly supported by Soitec and CEA LETI. | |
| dc.identifier.doi | 10.1109/iedm45741.2023.10413807 | |
| dc.identifier.issn | 2380-9248 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/59223 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | IEEE | |
| dc.source.conference | International Electron Devices Meeting (IEDM) | |
| dc.source.conferencedate | 2023-12-09 | |
| dc.source.conferencelocation | San Francisco | |
| dc.source.journal | 2023 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM | |
| dc.source.numberofpages | 4 | |
| dc.title | Ultimate Layer Stacking Technology for High Density Sequential 3D Integration | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2026-04-07 | |
| imec.internal.source | crawler | |
| imec.internal.wosCreatedAt | 2026-04-07 | |
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