Novel Design Strategy for High-Endurance (>10<SUP>10</SUP>) and Fast-Erase Oxide-Semiconductor Channel FeFET

Abstract

We fabricate ALD Oxide-Semiconductor Channel (OSC) FeFETs on 300-mm wafers. New design strategies of OSC FeFETs by La:HZO/IGZO interfacial engineering and IGZO channel thickness/length scaling are implemented to achieve high endurance and faster erase. The impact of IGZO composition is investigated, revealing that In-poor IGZO improves both the Memory Window (MW) and Vt stability. High MW and state-of-art endurance (>1010 cycles) are demonstrated in novel dual-composition-channel FeFETs. With all layers grown by ALD, this advanced stack is promising for the 3D integration of OSC FeFETs in high-endurance, low-latency, and non-destructive-read memories.