Design for manufacturability analysis in dual damascene 28nm-pitch single exposure EUV metal logic designs using voltage contrast

Abstract

In this work a method to characterize yield impact of different metal logic place and route (PnR) designs for pitch 28nm single exposure EUV is presented. By combining optimized test design structures with voltage contrast (VC) metrology it is possible to identify, in a systematic way, logic design variants with electrical open or short failures located at stochastic hotspots. This method can guide designers and process integration engineers to rapidly identify and rank the hotspots and therefore improve the designs and the manufacturability margin.