Publication:

Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications

Date

2011
Proceedings Paper
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dc.contributor.authorJourdain, Anne
dc.contributor.authorBuisson, Thibault
dc.contributor.authorPhommahaxay, Alain
dc.contributor.authorRedolfi, Augusto
dc.contributor.authorThangaraju, Sarasvathi
dc.contributor.authorTravaly, Youssef
dc.contributor.authorBeyne, Eric
dc.contributor.authorSwinnen, Bart
dc.contributor.imecauthorJourdain, Anne
dc.contributor.imecauthorPhommahaxay, Alain
dc.contributor.imecauthorRedolfi, Augusto
dc.contributor.imecauthorBeyne, Eric
dc.contributor.imecauthorSwinnen, Bart
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.accessioned2021-10-19T14:38:56Z
dc.date.available2021-10-19T14:38:56Z
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19141
dc.source.beginpage1122
dc.source.conferenceIEEE 61st Electronic Components and Technology Conference - ECTC
dc.source.conferencedate31/05/2011
dc.source.conferencelocationLake Buena Vista, FL US
dc.source.endpage1125
dc.title

Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications

dc.typeProceedings paper
dspace.entity.typePublication
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