A 70nm vertical Si/Si1-xGex heterojunction pMOSFET with reduced DIBL sensitivity for VLSI applications

dc.contributor.author	Verheyen, Peter
dc.contributor.author	Collaert, Nadine
dc.contributor.author	Caymax, Matty
dc.contributor.author	Loo, Roger
dc.contributor.author	De Meyer, Kristin
dc.contributor.author	Van Rossum, Marc
dc.contributor.imecauthor	Verheyen, Peter
dc.contributor.imecauthor	Collaert, Nadine
dc.contributor.imecauthor	Caymax, Matty
dc.contributor.imecauthor	Loo, Roger
dc.contributor.imecauthor	De Meyer, Kristin
dc.contributor.orcidimec	Collaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimec	Loo, Roger::0000-0003-3513-6058
dc.date.accessioned	2021-10-14T11:55:16Z
dc.date.available	2021-10-14T11:55:16Z
dc.date.embargo	9999-12-31
dc.date.issued	1999
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/4005
dc.source.conference	Silicon Nanoelectronics Workshop Abstracts
dc.source.conferencedate	12/06/1999
dc.source.conferencelocation	Kyoto Japan
dc.title	A 70nm vertical Si/Si1-xGex heterojunction pMOSFET with reduced DIBL sensitivity for VLSI applications
dc.type	Proceedings paper
dspace.entity.type	Publication
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