Publication:

Low track height standard cell design in iN7 using scaling boosters

Date

2017
Proceedings Paper
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dc.contributor.authorSherazi, Yasser
dc.contributor.authorJha, Chaitanya
dc.contributor.authorRodopoulos, Dimitrios
dc.contributor.authorDebacker, Peter
dc.contributor.authorChava, Bharani
dc.contributor.authorMattii, Luca
dc.contributor.authorGarcia Bardon, Marie
dc.contributor.authorSchuddinck, Pieter
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorGerousis, V.
dc.contributor.authorSpessot, Alessio
dc.contributor.authorVerkest, Diederik
dc.contributor.authorMocuta, Anda
dc.contributor.authorKim, Ryan Ryoung han
dc.contributor.authorRyckaert, Julien
dc.contributor.imecauthorSherazi, Yasser
dc.contributor.imecauthorDebacker, Peter
dc.contributor.imecauthorGarcia Bardon, Marie
dc.contributor.imecauthorSchuddinck, Pieter
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorKim, Ryan Ryoung han
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.accessioned2021-10-24T13:25:43Z
dc.date.available2021-10-24T13:25:43Z
dc.date.embargo9999-12-31
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/29425
dc.identifier.urlhttp://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=2613289
dc.source.beginpage101480Y
dc.source.conferenceDesign-Process-Technology Co-optimization for Manufacturability XI
dc.source.conferencedate26/02/2017
dc.source.conferencelocationSan Jose, CA USA
dc.title

Low track height standard cell design in iN7 using scaling boosters

dc.typeProceedings paper
dspace.entity.typePublication
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