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Surround Gate Transistor With Epitaxially Grown Si Pillar and Simulation Study on Soft Error and Rowhammer Tolerance for DRAM

 
dc.contributor.authorHan, Jin-Woo
dc.contributor.authorKim, Jungsik
dc.contributor.authorBeery, Dafna
dc.contributor.authorBozdag, K. Deniz
dc.contributor.authorCuevas, Peter
dc.contributor.authorLevi, Amitay
dc.contributor.authorTain, Irwin
dc.contributor.authorTran, Khai
dc.contributor.authorWalker, Andrew J.
dc.contributor.authorVadakupudhu Palayam, Senthil
dc.contributor.authorArreghini, Antonio
dc.contributor.authorFurnemont, Arnaud
dc.contributor.authorMeyappan, M.
dc.contributor.imecauthorVadakupudhu Palayam, Senthil
dc.contributor.imecauthorArreghini, Antonio
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.orcidextHan, Jin-Woo::0000-0002-5118-1310
dc.contributor.orcidextKim, Jungsik::0000-0001-7798-3381
dc.contributor.orcidextWalker, Andrew J.::0000-0001-7842-061X
dc.contributor.orcidimecPalayam, Senthil Vadakupudhu::0000-0002-0855-3377
dc.contributor.orcidimecArreghini, Antonio::0000-0002-7493-9681
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.date.accessioned2022-12-01T09:32:14Z
dc.date.available2021-11-02T16:04:30Z
dc.date.available2022-05-20T07:46:06Z
dc.date.available2022-06-28T14:46:23Z
dc.date.available2022-12-01T09:32:14Z
dc.date.issued2021
dc.identifier.doi10.1109/TED.2020.3045966
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/38144
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage529
dc.source.endpage534
dc.source.issue2
dc.source.journalIEEE TRANSACTIONS ON ELECTRON DEVICES
dc.source.numberofpages6
dc.source.volume68
dc.title

Surround Gate Transistor With Epitaxially Grown Si Pillar and Simulation Study on Soft Error and Rowhammer Tolerance for DRAM

dc.typeJournal article
dspace.entity.typePublication
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