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Admittance matrix calculations of on-chip interconnects on lossy silicon substrate using multilayer Green's function

Date

2001
Proceedings Paper
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dc.contributor.authorYmeri, Hasan
dc.contributor.authorNauwelaers, Bart
dc.contributor.authorMaex, Karen
dc.contributor.authorDe Roest, David
dc.contributor.authorVandenberghe, S.
dc.contributor.authorStucchi, Michele
dc.contributor.imecauthorNauwelaers, Bart
dc.contributor.imecauthorMaex, Karen
dc.contributor.imecauthorDe Roest, David
dc.contributor.imecauthorStucchi, Michele
dc.date.accessioned2021-10-14T18:29:21Z
dc.date.available2021-10-14T18:29:21Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5861
dc.source.beginpage50
dc.source.conferenceTopical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2001. Digest of Papers
dc.source.conferencedate12/09/2001
dc.source.conferencelocationAnn Arbor, MI USA
dc.source.endpage59
dc.title

Admittance matrix calculations of on-chip interconnects on lossy silicon substrate using multilayer Green's function

dc.typeProceedings paper
dspace.entity.typePublication
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