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Layout impact on the performance of a locally strained PMOSFET

dc.contributor.authorEneman, Geert
dc.contributor.authorVerheyen, Peter
dc.contributor.authorRooyackers, Rita
dc.contributor.authorNouri, Faran
dc.contributor.authorWashington, Lori
dc.contributor.authorDegraeve, Robin
dc.contributor.authorKaczer, Ben
dc.contributor.authorMoroz, Victor
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorSchreutelkamp, Rob
dc.contributor.authorKawaguchi, M.
dc.contributor.authorKim, Y.
dc.contributor.authorSamoilov, A.
dc.contributor.authorSmith, L.
dc.contributor.authorAbsil, Philippe
dc.contributor.authorDe Meyer, Kristin
dc.contributor.authorJurczak, Gosia
dc.contributor.authorBiesemans, Serge
dc.date.accessioned2021-10-16T01:30:33Z
dc.date.available2021-10-16T01:30:33Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10431
dc.sourceIIOimport
dc.titleLayout impact on the performance of a locally strained PMOSFET
dc.typeProceedings paper
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorVerheyen, Peter
dc.contributor.imecauthorDegraeve, Robin
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorAbsil, Philippe
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.imecauthorBiesemans, Serge
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.source.peerreviewno
dc.source.beginpage22
dc.source.endpage23
dc.source.conferenceSymposium on VLSI Technology. Digest of Technical Papers
dc.source.conferencedate14/06/2005
dc.source.conferencelocationKyoto Japan
imec.availabilityPublished - imec


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