Show simple item record

Characterization and otimalization of 65nm CMOS technology using scanning spreading resistance microscopy

dc.contributor.authorEyben, Pierre
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorChramtsov, I.
dc.contributor.authorFouchier, M.
dc.contributor.authorJanssens, Tom
dc.contributor.authorVandervorst, Wilfried
dc.date.accessioned2021-10-16T01:32:56Z
dc.date.available2021-10-16T01:32:56Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10444
dc.sourceIIOimport
dc.titleCharacterization and otimalization of 65nm CMOS technology using scanning spreading resistance microscopy
dc.typeMeeting abstract
dc.contributor.imecauthorEyben, Pierre
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorVandervorst, Wilfried
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.source.peerreviewno
dc.source.beginpage55
dc.source.conferenceProceedings of the 8th Int. Workshop on the Fabrication , Characterization and Modeling of Ultra Shallow Junctions in Semicond.
dc.source.conferencedate5/06/2005
dc.source.conferencelocationDaytona Beach, FL USA
imec.availabilityPublished - imec


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following collection(s)

Show simple item record