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Process optimization of low temperature silicon nitride stressor layers for improvement of device performance for 45nm technology and below
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Process optimization of low temperature silicon nitride stressor layers for improvement of device performance for 45nm technology and below
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Date
2005
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Eyckens, Brenda
;
Collaert, Nadine
;
Schaekers, Marc
;
Sleeckx, Erik
;
Eneman, Geert
;
Verheyen, Peter
;
Rooyackers, Rita
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1926
since deposited on 2021-10-16
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Acq. date: 2025-12-16
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Metrics
Views
1926
since deposited on 2021-10-16
1
last month
Acq. date: 2025-12-16
Citations