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Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

dc.contributor.authorKittl, Jorge
dc.contributor.authorVeloso, Anabela
dc.contributor.authorLauwers, Anne
dc.contributor.authorKottantharayil, Anil
dc.contributor.authorDemeurisse, Caroline
dc.contributor.authorKubicek, Stefan
dc.contributor.authorNiwa, Masaaki
dc.contributor.authorVan Dal, Mark
dc.contributor.authorRichard, Olivier
dc.contributor.authorKmieciak, Malgorzata
dc.contributor.authorJurczak, Gosia
dc.contributor.authorVrancken, Christa
dc.contributor.authorChiarella, Thomas
dc.contributor.authorBrus, Stephan
dc.contributor.authorMaex, Karen
dc.contributor.authorBiesemans, Serge
dc.date.accessioned2021-10-16T02:33:51Z
dc.date.available2021-10-16T02:33:51Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10702
dc.sourceIIOimport
dc.titleScalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths
dc.typeProceedings paper
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorLauwers, Anne
dc.contributor.imecauthorDemeurisse, Caroline
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorVan Dal, Mark
dc.contributor.imecauthorRichard, Olivier
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.imecauthorVrancken, Christa
dc.contributor.imecauthorChiarella, Thomas
dc.contributor.imecauthorBrus, Stephan
dc.contributor.imecauthorMaex, Karen
dc.contributor.imecauthorBiesemans, Serge
dc.contributor.orcidimecRichard, Olivier::0000-0002-3994-8021
dc.contributor.orcidimecChiarella, Thomas::0000-0002-6155-9030
dc.source.peerreviewno
dc.source.beginpage72
dc.source.endpage73
dc.source.conferenceSymposium on VLSI Technology. Digest of Technical Papers
dc.source.conferencedate12/06/2005
dc.source.conferencelocationKyoto Japan
imec.availabilityPublished - imec


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