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Charge trapping effects and interface state generation in a 40V lateral resurf pDMOS transistor

dc.contributor.authorMoens, Peter
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorWojciechowski, Dominique
dc.contributor.authorBauwens, Filip
dc.contributor.authorDe Vleeschouwer, Herbert
dc.contributor.authorDe Pestel, Freddy
dc.date.accessioned2021-10-16T03:29:23Z
dc.date.available2021-10-16T03:29:23Z
dc.date.issued2005-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10897
dc.sourceIIOimport
dc.titleCharge trapping effects and interface state generation in a 40V lateral resurf pDMOS transistor
dc.typeProceedings paper
dc.contributor.imecauthorMoens, Peter
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.source.peerreviewyes
dc.source.beginpage407
dc.source.endpage410
dc.source.conferenceProceedings of the 35th European Solid-State Device Research Conference - ESSDERC
dc.source.conferencedate12/09/2005
dc.source.conferencelocationGrenoble France
imec.availabilityPublished - imec


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