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The impact of layout on stress-enhanced transistor performance

dc.contributor.authorMoroz, Victor
dc.contributor.authorEneman, Geert
dc.contributor.authorVerheyen, Peter
dc.contributor.authorNouri, Faran
dc.contributor.authorWashington, Lori
dc.contributor.authorSmith, Lee
dc.contributor.authorJurczak, Gosia
dc.contributor.authorPramanik, Dipu
dc.date.accessioned2021-10-16T03:32:15Z
dc.date.available2021-10-16T03:32:15Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10907
dc.sourceIIOimport
dc.titleThe impact of layout on stress-enhanced transistor performance
dc.typeProceedings paper
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorVerheyen, Peter
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.source.peerreviewno
dc.source.beginpage143
dc.source.endpage146
dc.source.conferenceProceedings of the International Conference on Simulation of Semiconductor Processes and Devices - SISPAD
dc.source.conferencedate1/09/2005
dc.source.conferencelocationTokyo Japan
imec.availabilityPublished - imec


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