dc.contributor.author | Moroz, Victor | |
dc.contributor.author | Eneman, Geert | |
dc.contributor.author | Verheyen, Peter | |
dc.contributor.author | Nouri, Faran | |
dc.contributor.author | Washington, Lori | |
dc.contributor.author | Smith, Lee | |
dc.contributor.author | Jurczak, Gosia | |
dc.contributor.author | Pramanik, Dipu | |
dc.date.accessioned | 2021-10-16T03:32:15Z | |
dc.date.available | 2021-10-16T03:32:15Z | |
dc.date.issued | 2005 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/10907 | |
dc.source | IIOimport | |
dc.title | The impact of layout on stress-enhanced transistor performance | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Eneman, Geert | |
dc.contributor.imecauthor | Verheyen, Peter | |
dc.contributor.imecauthor | Jurczak, Gosia | |
dc.contributor.orcidimec | Eneman, Geert::0000-0002-5849-3384 | |
dc.source.peerreview | no | |
dc.source.beginpage | 143 | |
dc.source.endpage | 146 | |
dc.source.conference | Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices - SISPAD | |
dc.source.conferencedate | 1/09/2005 | |
dc.source.conferencelocation | Tokyo Japan | |
imec.availability | Published - imec | |