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Study of stress evolution during full silicidation for gate stacks

dc.contributor.authorTorregiani, Cristina
dc.contributor.authorKittl, Jorge
dc.contributor.authorCapponi, Simona
dc.contributor.authorVanhoyland, Geert
dc.contributor.authorBrongersma, Sywert
dc.contributor.authorLauwers, Anne
dc.contributor.authorVan Houtte, Paul
dc.contributor.authorMaex, Karen
dc.date.accessioned2021-10-16T05:46:26Z
dc.date.available2021-10-16T05:46:26Z
dc.date.issued2005-05
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11329
dc.sourceIIOimport
dc.titleStudy of stress evolution during full silicidation for gate stacks
dc.typeProceedings paper
dc.contributor.imecauthorBrongersma, Sywert
dc.contributor.imecauthorLauwers, Anne
dc.contributor.imecauthorMaex, Karen
dc.contributor.orcidimecBrongersma, Sywert::0000-0002-1755-3897
dc.source.peerreviewno
dc.source.beginpage249
dc.source.endpage256
dc.source.conferenceAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment
dc.source.conferencedate15/05/2005
dc.source.conferencelocationQuebec Canada
imec.availabilityPublished - imec
imec.internalnotesElectrochemical Society Proceedings; Vol. 2005-05


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