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Electrical performance and reliability aspects of strain engineered deep submicron CMOS technologies

dc.contributor.authorClaeys, Cor
dc.contributor.authorEneman, Geert
dc.contributor.authorBargallo Gonzalez, Mireia
dc.contributor.authorPut, Sofie
dc.contributor.authorSimoen, Eddy
dc.date.accessioned2021-10-16T15:19:33Z
dc.date.available2021-10-16T15:19:33Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11875
dc.sourceIIOimport
dc.titleElectrical performance and reliability aspects of strain engineered deep submicron CMOS technologies
dc.typeProceedings paper
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage15
dc.source.endpage22
dc.source.conferenceInt. Conf. on Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors (ULSIC vs. TFT)
dc.source.conferencedate28/07/2007
dc.source.conferencelocationBarga Italy
imec.availabilityPublished - open access
imec.internalnotesECS Trans.; Vol. 8, Issue 1


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