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Grinding and mixed silicon copper CMP of stacked patterned wafers for 3D integration

dc.contributor.authorDe Munck, Koen
dc.contributor.authorVaes, Jan
dc.contributor.authorBogaerts, Lieve
dc.contributor.authorDe Moor, Piet
dc.contributor.authorVan Hoof, Chris
dc.contributor.authorSwinnen, Bart
dc.date.accessioned2021-10-16T15:32:58Z
dc.date.available2021-10-16T15:32:58Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11967
dc.sourceIIOimport
dc.titleGrinding and mixed silicon copper CMP of stacked patterned wafers for 3D integration
dc.typeProceedings paper
dc.contributor.imecauthorDe Munck, Koen
dc.contributor.imecauthorBogaerts, Lieve
dc.contributor.imecauthorDe Moor, Piet
dc.contributor.imecauthorVan Hoof, Chris
dc.contributor.imecauthorSwinnen, Bart
dc.source.peerreviewno
dc.source.beginpage275
dc.source.endpage280
dc.source.conferenceEnabling Technologies for 3-D Integration
dc.source.conferencedate26/11/2006
dc.source.conferencelocationBoston, MA USA
imec.availabilityPublished - imec
imec.internalnotesMRS Symposium Proceedings; Vol. 970


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